Principal Engineer

Hello,

You have bright career with leading product based MNC across India. Send your updated resume ASAP.

JD for Lattice is below :

Accountabilities as Principal Engineer :

• Lead the design and development of FPGA debug engine in Lattice EDA suite.
• Architect and refactor the FPGA debug IP and guide the UI team to enhance existing functionality and new features.
• As a principal RTL Engineer, you will work closely with marketing requirements and generate functional architecture and specifications for new FPGA debug IP functionality and guide the QA teams and ensure that implementations match design intent.
• Mentor and guide junior RTL & UI engineers working on FPGA debug IP, fostering a culture of continuous improvement and innovation.
• Maintain high standards of architecture, implementation quality, performance, and reliability.
• Improve development methodologies and processes.

Qualifications

Education

Masters in Technology (M.Tech / M.E), Bachelor Of Technology (B.Tech / B.E)

Skills Required

Fpga, RTL, Debugging