Who are we and what do we do?
The HVP team in TI develops power solutions for a wide array of end equipment’s, with several hundreds of volts of withstand capability.This team in TI offers one of the world's largest comprehensive portfolios of high-performance AC / DC and isolated DC / DC controllers, converters and modules with the widest range of power topology options.
Within HVP, High Voltage Controllers (HVC) is an exciting group looking to develop smart power controller products for cutting-edge high-voltage industrial and automotive applications and demonstrate the significant performance benefits of TI’s technologies.
GaN is a wide-bandgap semiconductor technology which offers the potential to revolutionize the power semiconductor market by enabling significantly higher power density than existing silicon-based alternatives. Also within HVP, the GaN team is fighting in a new & fast-growing market against established competitors & emerging start-ups to be the #1 GaN power supplier.
This is a new investment area for TI in India, and the candidate will get to be part of an exciting startup-like ecosystem, getting the experience of building a team and technical expertise under the safety of the wider TI umbrella.
What will you be doing in this role? (Responsibilities)
Be a key team member from product definition till release to market, working closely with all functions (e.g. systems, analog design, verification, test, applications).
Define or enhance the micro-architecture for digital blocks / top and designing them along with rest of the team.
RTL development and verification (RTL and Gate level).
Collaborate with Systems engineers, analog designers on mixed-signal and DSP blocks and interfaces.
Work closely with verification team to build the full-chip verification plan, tests. Support functional debugs and RCAs.
Support silicon validation activities, test program development and the customer engagement and silicon / application debug needs.
Drive architectural optimization for area, power and performance improvements for a given node.
Address performance bottlenecks through micro-architecture.
Experience in managing small teams
What do we expect from you? (Mini Qualifications)
Knowledge and Skills
Hands on front-end design experience of complex multi clock domain blocks.
Ability to convert high level system requirements / changes into micro-architectural changes and then into RTL
Ability to extract the functionality / micro-architecture of existing design even with sparse legacy documentation
Familiarity with verification environments to be able to actively participate in functional debugs
Good knowledge on static timing analysis and constraints debugging.
Understand and own in detail the functional specifications of the IPs / SoC
Ensure that design-for-test (DFT) standards are addressed by design
Participate in and conduct design reviews. Create the necessary design documentation
Ability to take initiatives and drive the results working with team members across time-zones
Handling & owning design deliverables and schedule
Bachelors / Masters in Electrical / Electronics Engineering
Other
Good team player, attitude and thirst for continuous learning
Strong communication and interpersonal skills
Ability to function independently, be self-driven
Preferred Skills / Experience
8-15 years of relevant experience
Excellent RTL design (Verilog) skill including Lint, Simulation, Debug, Synthesis and LEC (preferably Cadence toolchain).
Experience in identifying and implementing complex ECO in netlist.
Experience in writing and debugging timing constraints at IP / SoC level
Experience in silicon functional debug / RCA to map bugs to RTL. Familiarity with Si-bringup & Bench testing
Experience in FPGA prototyping of full / parts of system would be a plus.
Expertise in automation using Python / Perl / Tcl / shell scripting
Experience in managing small teams
Experience in AES, SHA, TRNG and Trustzone architectures.
Experience in system definition with Security architectures like Trustzone, Secure boot, etc.
Soc Manager • Bengaluru, India