Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asksAbility to come with detailed test plan based on the Arch specsGood understanding and exposure to SoC design and architecture10+ years of Design Verification experience with strong Verilog, System Verilog, C and UVM / OVM knowledgeCandidate should be able to develop Testbench. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage & assertions.Own the DV sign-off and ensure a bug free designWork with the post-silicon team on debug support and to help root-cause any failuresHave worked on wireless protocol design verificationBringing up Testbench / SoC verification environment. Good understanding of SoC RESET / CLOCK flowExposure to DEBUG concepts such as JTAG etcComfortable with VCS / Verdi and excellent debug skillsLogical in thinking and ability to gel well within a teamGood communication skillsContinuously drive methodology improvements to improve efficiencyMentor junior engineers to build a high performing teamPREFERRED EXPERIENCE :
- Proficient in SoC / sub-system / IP level ASIC verification
- Proficient in debugging firmware and RTL code using simulation tools
- Proficient in using UVM testbenches
- Experienced with Verilog, System Verilog, C, and C++
- Worked on any High Speed Interface like PCIE / DDR / USB / Other, Good understanding of AXI / AHB / APB Bus protocol
- Prior knowledge of ARM / RISC Processor based designs verification and bring-up verification
- Developing UVM based verification frameworks and testbenches, processes and flows
- Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
- Scripting language experience : Perl, Python, Makefile, shell preferred.
Skills Required
Python Scripting, SOC design, SoC Verification, System Verilog