Semiconductor Layout Engineer

Memory Layout Design : Create and optimize physical layouts for memory components (e.G., SRAM, DRAM, ROM) using advanced EDA tools like Synopsys Custom Compiler or other industry-standard tools. Ensure that the memory design meets specifications for area, power, performance, and manufacturability.

Memory Optimization : Work on layout optimizations for area, speed, and power consumption. Collaborate with design and architecture teams to implement memory features that enhance the overall system performance.

Design Rule Checks (DRC) & Layout Versus Schematic (LVS) : Perform thorough design rule checks (DRC) and layout versus schematic (LVS) checks to ensure that memory layouts comply with foundry design rules and pass all required checks before tape-out.