STA Lead [03 / 10 / 2025]

Skills Required

• Netlist and constraint sign in checks and validation.
• Prime time constraint development at full chip level and clean up.
• Multimode multi corner timing knowledge and timing closure at sub HM / block / top level.
• Top level timing closure with sign off STA in MMMC with Xtalk and OCV. Top level ECO implementation strategy development for netlist, RTL and timing level changes Scripting experience in Perl / TCL.
• Excellent debugging skills in implementation issues and ability to come up with creative solutions .
• Technologies from 28nm and below.
• Need minimum 8+ yoe
• Has to be good in Synthesis & STA, with timing constraints expertise
• Primetime or Tempus - both are okay.
• Available within 30 days