Senior DFT Engineer

Responsibilities

Develop and implement Design for Test (DFT) methodologies for IoT products.

Collaborate with design and backend teams to integrate DFT features.

Create and validate test plans to ensure thorough coverage and fault detection.

Support silicon bring-up and debug activities.

Automate test processes such as ATPG / MBIST to enhance efficiency and accuracy.

Test coverage analysis and improve test coverage to sign-off IJTAG cores, SoC.

Qualifications

Bachelor's in Electrical & Electronics / ECE or master’s degree in VLSI.

4+ years of experience in DFT, ASIC design.

Experience with DFT tools such as Tessent, Genus and Validation with Questa, Xcelium tools preferred.

Solid understanding of digital design concepts and Simulations.

Strong analytical and problem-solving skills.

Good communication and teamwork skills.

Skills

Scan insertion, DRC fixes.

Boundary scan

ATPG (Automatic Test Pattern Generation)

JTAG (Joint Test Action Group)

MBIST (Memory Built-In Self-Test) insertion and DRC fixes.

Verilog / VHDL

Scripting languages (Perl, TCL, Python)

DFT tools (Siemens Tessent shell, Synopsys TetraMAX, Cadence Genus)

Validation tools (Siemens Questa, Cadence Xcelium, etc).