DFT Engineer

#Urgent_Opening_for_Canvendor

#Hiring : DFT Engineer (3+ Years Experience) |Bangalore| Immediate Joiners Preferred

Location : Bangalore, India

Experience : 3-8 Years

Notice period : Immediate to 30days

Mandatory : DFT, ATPG, Scan Insertion, EDA Tools

#Key_Requirements :

DFT Fundamentals including JTAG, Scan, ATPG, IEEE 1687 iJTAG, EDT Architecture

Scan Insertion using Fusion Compiler or other EDA tools

ATPG Coverage Analysis and DRC clean up

ATPG patterns simulation and debug using SNPS VCS and Verdi tools

Understanding of Design for Test methodologies and DFT experience (e.g. JTAG 1149.x, IEEE 1500, IEEE 1687 iJTAG, Scan, ATPG, Memory BIST, etc.)

Familiar with DFT flow and EDA tools, including Fusion Compiler, Synopsys Tmax or Mentor Testkompress / Tessent, SSN, etc.

Experienced with Verilog, System Verilog, VCS simulation tool, Perl / Shell scripting, and Verilog RTL design

Experience in debugging Compressed ATPG patterns, MBIST, and JTAG / 1500 related issues

Experience in test failures debug to determine the root cause; work with design engineers to resolve design defects and correct any test issues

Experience with STA constraints development, analysis for DFT modes and SDF simulations

Good communication skills

If interested kindly share your updated CV to anushab@canvendor.com