Digital Verification

We Are Hiring – DV Engineer (SV / UVM) | Immediate Start | India (Remote / Hybrid / On-site)

We are looking for an experienced Design Verification Engineer to join our client’s long-term semiconductor project (company name confidential).

Experience : Minimum 5+ years

Location : India – Remote / Hybrid / On-site options available

⏳ Duration : Long-term

Start Date : Immediate

Key Skills Required

• Strong hands-on experience in SystemVerilog (SV) and UVM
• Expertise in testbench development, test plans, and testcase creation
• Solid understanding of UFS protocols (UFS3 / UFS4 / UFS5)
• Experience in debugging, coverage, and verification methodologies
• Ability to work independently and collaborate with cross-functional teams

What We Offer

If you’re interested, please DM me or share your updated profile at

Referrals are always appreciated!