Senior / Lead Static Timing Analysis Engineer

We are seeking an experienced, highly motivated and high-caliber individual to build these differentiating products. Does this sound like a good role for you

• Senior / Lead STA Engineer (R&D Engineering)
• Location : Hyderabad & Bhubaneswar & Bangalore
• Experience : 5yrs to 15yrs
• Strong experience in STA concepts , tools and methodologies at IP / subsystem / chip levels
• Hands-on experience in Synthesis, pre-layout STA, post-layout STA, CTS tools
• Ability to understand IP / subsystem design and come up with STA plan / checkers and reviews
• Sound knowledge of standard ASIC RTL2GDS physical implementation and signoff flows
• Exposure to design implementation and signoff of soft & mixed-signal IPs and subsystems
• Experience in Functional, DFT (scan-shift, scan-capture and at-speed) mode constraints development and timing closure with MCMM (multi-corner, multi-mode)
• Proficiency with Backend & STA tools from any EDA vendor, preferably Synopsys tools like PrimeTime, ICC2, Design Compiler, Fusion Compiler (or equivalent) used in the RTL2GDSII implementation
• Good understanding of OCV, POCV, derates, crosstalk and design margins
• Experience with design methodologies like developing custom scripts and enhancing flows for better execution. Experience in scripting with TCL / PERL is required
• Exposure to design implementation and signoff of soft & mixed-signal IPs and subsystems

Please share your updated CV with [HIDDEN TEXT] or refer those who would like to explore this opportunity.

Skills Required

crosstalk , Perl