Digital Design Engineer -Sr Lead

Requirements :

• Looking for a candidate with 1 to 3 years of hands-on experience in micro-architecting and developing complex IPs.
• Expertise in digital design, VLSI concepts, and experience in creating power / area-efficient IPs across multiple clock domains are essential.
• Proficiency in RTL coding and familiarity with RTL QA flows such as PLDRC, CDC, and CLP (optional) is expected.
• Candidates should be capable of proposing design alternatives to meet area / power / performance specifications and presenting these options for review.
• Experience in leading, guiding, or managing junior team members is advantageous.
• Repeated success in taking IP designs from requirements to silicon is required.
• While not mandatory, having developed IPs for wireless technologies (WLAN, LTE, NR, BT, UWB, etc.) or past HLS experience would be beneficial.

Skills :

• Must have :   Proficient in Verilog RTL coding, uArch, CDC check, PLDRC, Timing constraints, Python / Perl. Experience in design / debugging complex data-path / control-path IPs. Good communication, analytical & leadership skills.
• Good to have :   System Verilog, Visio, Knowledge of signal processing concepts / algorithms and Wi-Fi standards (802.11a / b / g / n / ac / ax), experience with HLS.

Minimum Qualifications :

• Bachelors degree in Computer Science, Electrical / Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
• OR
• Masters degree in Computer Science, Electrical / Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
• OR
• PhD in Computer Science, Electrical / Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Skills Required

Vlsi, Verilog, Signal Processing, RTL, Python