Principal Engineer

Strong experience in Logic Equivalence Check (LEC) and Low Power Checks (CLP) at block and SoC level designs

Job Description

In your new role you will :

• Implement high-performance, low-power, and area-efficient digital designs.
• Write and implement block level and top-level constraints for Synthesis, Static Timing Analysis.
• Optimize designs for power, performance, and area, and meet PPA goals.
• Power analysis using PT-PX or equivalent flow.
• Logic Equivalence Check (LEC) and Low Power Checks (CLP) at block and SoC level designs.
• Define and evaluate constraints and signoff Test / DFT mode timing requirement

Your Profile

You are best equipped for this task if you have :

Contact : [HIDDEN TEXT]

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Skills Required

Synthesis