Summary:
We are looking for Experienced Analog Mixed-Signal Layout Engineer with 24 years of expertise in PLL Oscillator Data Converter Power Management and IO IP layouts across advanced technology nodes (5nm40nm). Strong proficiency in Cadence Virtuoso analog layout techniques ESD reviews EM/IR analysis and cross-functional collaboration with global design and SoC teams to deliver high-quality IP layouts
Job Qualification:
Bachelors Degree in Electronic Engineering/ Electrical Engineering or equivalent.
1-3 years hands-on experience in Analog MSIP design/verification.
Working experience of layout done for Phase Locked Loops (PLL) Crystal Oscillators (XOSC) bias generators reference circuits Low Drop-Out regulators (LDO) IRCs high speed/general IOs Data converters.
Have exposure of doing layout in 5nm 16ffc 22fdx 28nm 40nm tech nodes
Have know-how of layout matching common centroid layout EM/IR analysis IO pad ring.
Worked on Cadence Virtuoso tool
Knowledge of back-end view generation like LEF ndm and milkyway.
Job Responsibility:
Work closely with design team to understand the scope of work. Available for the layout of high/low speed IOs and Clocking IP ( Crystal Oscillator PLL DPLL IRC) or Data Converter or Power Management IPs.
Available for the collaboration with our ACC team at Eindhoven Austin France and Noida.
Regular support and Interaction with the SoC team to understand their requirement.
Conducting ESD and layout reviews of the blocks/IPs at different interval of the design cycle
Ready to work for small sub blocks to complex top level IP layout. Expected to perform EM/IR analysis wherever required.
More information about NXP in India...
Required Experience:
IC
Analog Layout Engineer • Noida, Uttar Pradesh, India
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