Hardware Verification Engineer
L&T Technology ServicesBengaluru, Republic Of India, IN30+ days ago
Job descriptionBachelor or Master degree preferred from an accredited engineering school. 6-12 years of experience working in an SoC Chip level / Cluster / Sub-System Verification Experience in Microcontroller and Microprocessor architecture, ARM Cores, Interconnect (NIC, NoC), Cache Coherency, CPU / DSP / Multimedia / Peripheral blocks DV Env development for RTL verification, Gate Level (GLS) Verification and Timing (SDF) GLS verification with Synopsys / Mentor or Cadence or equivalent tools is required. Familiarity with different test pattern formats such as STIL, WGL, SVF, VCD, eVCD and ATE fail datalogs. Experience on ATE pattern generation / conversion, Virtual Tester simulation and Bench CSV generation is required. Familiarity with JTAG / APB / AHB / AXI based protocols and experience with design and debug of functional / AMS / HSIO patterns on ATE / Bench Partner with ATE team on Silicon Debug and ensure the patterns stability across voltage / temperature / process corners. HVL methodology (UVM / OVM / VMM) and HDL (System Verilog, Verilog) is a plus. Experience with scripting languages like Python, Perl, skill, tcl or equivalent to automate flows is a plus.
Dear Linkedin reader,
We are constantly looking out for right VLSI talent to join our team.
JOB RESPONSIBILITIES :
- Job responsibilities include working with the SoC Development teams to verify / simulate / debug CPU(ARM,RISC-V) / GPU / DSP / Multimedia / Peripheral / AMS / HSIO blocks RTL / Gate level, ATE / Bench pattern generation with target coverage and Silicon Debug.
- Candidates must be familiar with the SoC level DV / UVM environment, JTAG / APB / AHB / AXI based protocols and the requirements for verifying SubSystems on SOC level.
REQUIREMENTS :
Regards,
Sreenath Vijayan
sreenath.vijayan@ltts.com
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Verification Engineer • Bengaluru, Republic Of India, IN
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