RTL Design
Location : Bangalore
Experience- 4+ years
Must have
- Hands-on experience and expert-level knowledge in RTL design and coding in Verilog and VHDL
- Hands-on experience and expert-level knowledge in SoC integration of ARM core-based designs
- Experience in working with AMBA Bus- AXI, AHB, APB.
- Experience in IP development : Standard Ips like PCIe Gen5 or Gen6, USB4.x, Ethernet, UCIe, HBM
- Hands-on experience and expert-level knowledge in ASIC Synthesis
- Hands-on Experience with Lint and CDC.
- Experience in equivalency checking
- Experience with FPGA based designs or FPGA prototyping
- In-depth understanding of Verilog / VHDL and ARM SoC architecture
- Hands-on experience and expert-level knowledge in Static Timing Analysis
Educational Qualification : BE / ME or BTech / MTech
Preferred
Experience in Ethernet, PCIeExperience in the networking domainExperience in PERL, TCL. PythonTools – Cadence / Synopsys toolsets