Job descriptionMinimum of 10+ years of experience in DFT implementationProven experience in implementing DFT techniques such as scan insertion, MBIST, BIST, JTAG, OCC, EDT etcDevelop DFT strategy and architecture, including hierarchical DFT.Experience in JTAG and iJTAG protocols and architectures.ATPG pattern generation, ATPG patterns verification with gate-level simulationMBIST pattern generation, Pattern simulations with gate-level simulationsBIST implementation for both AC & DC pinsExperience working in Partition / Block / SoC level designsExperience in working with SSN implementation and verification.Experience in DFT Flows brings up from scratch (Script implementation)Experience with EDA tools for DFT (e.g., Siemens Mentor)Effective communication and leadership skillsCollaborate with cross-functional teams to ensure DFT requirements are met