Abstraction expertise like Hyperscale / ILM / ETM.
RC Balancing and scaling analysis of full chip clock.
RC Balancing and scaling analysis of critical data paths.
Good automation skills in PERL, TCL and EDA tool-specific scripting.
DMSA @ full chip and custom scripts for timing fixes
Qualification :
BE / BTECH / MTECH in EE / ECE with proven experience in ASIC Physical Design.
Detailed knowledge of EDA tools and flows, Tempus / Primetime experience is must.
Experience – 7+ years.
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Lead • Bengaluru, Karnataka, India
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