Senior / Staff Engineer, Physical Design(Clocking)

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

We’re looking for an experienced engineer to lead the clock design efforts across our IP, CPU, and SoC teams. In this role, you’ll define clocking strategies that balance tight timing, power, and area goals—while working side by side with RTL, PD, and power engineers to build robust, high-performance systems.

This role is onsite, based out of Bangalore.

We welcome candidates with 6+ years of experience for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are :

You have a strong background in clock tree synthesis and clock network design.

You’re comfortable working with timing, CDC, and low-power design techniques.

You’ve worked on advanced technology nodes (5nm or below) and know how they shape design choices.

You enjoy writing scripts to automate tasks and improve engineering workflows.

What We Need :

Someone who can own the end-to-end clock architecture across complex SoCs.

The ability to collaborate with RTL, physical design, and power teams to get the job done.

Experience with tools like Synopsys FC, ICC2, and scripting in Python, Perl, or Tcl.

A problem-solver who thrives on making things more efficient and robust.

What You Will Learn :

How to architect clocking strategies that scale across IP, CPU, and SoC designs.

Techniques to reduce power and jitter while meeting aggressive PPA targets.

Ways to improve flows and reduce manual effort through smart automation.

How to navigate and solve challenges specific to cutting-edge technology nodes.