RFIC AMS DV Sr Engineer

General Summary :

Join Qualcomm's world-class Hardware Engineering team, where we push the limits of technology to enable cutting-edge experiences for a smarter, more connected future. We are seeking a Hardware Verification Engineer with experience in SystemVerilog modeling and mixed-signal verification to support design validation for advanced WAN and GPS radio modules used in 5G chipsets.

This role involves developing real-number models , functional verification environments , and working with AMS simulation flows to ensure performance and functionality of complex SoC designs involving RF, analog, and digital components.

Key Responsibilities :

• Develop SystemVerilog real-number models (RNM) for analog and RF blocks used in WAN and GPS subsystems.
• Create and execute functional verification plans for mixed-signal SoC modules.
• Build UVM / SystemVerilog-based testbenches , write self-checking test cases, and perform regression testing , debugging , functional coverage analysis , and bug tracking .
• Perform AMS simulations using SPICE-level tools (e.g., Spectre) and digital simulators in co-simulation environments.
• Work with Cadence toolsets including Virtuoso, SimVision, and NC-Sim for modeling, debugging, and simulation.
• Collaborate with cross-functional teams including RFIC / Analog Design , Digital Verification , and DFT Engineers to ensure robust SoC verification.
• Support post-silicon bring-up and validation for taped-out chips.
• Automate simulation and verification flows using Perl, Python, and Shell scripting .

Minimum Qualifications :

Preferred Skills & Experience :

Soft Skills :

Skills Required

Python, Gpo, AMs, Uvm, hardware engineering , ASIC Design, System Verilog