(06 / 11 / 2025) Senior Design Verification Engineer

AMS Verification Engineer Experience : 3+ years Location : Bangalore The role involves working on real number modeling and verification of mixed-signal designs using System Verilog and UVM methodologies. This is a hands-on opportunity to gain experience in advanced verification flows and contribute to real-world projects. Key Responsibilities : Develop and validate real number models (WREAL) for analog / mixed-signal blocks. Integrate real number models into digital verification environments. Write and maintain SystemVerilog / UVM testbenches. Perform functional and regression testing of mixed-signal IPs. Collaborate with design and verification engineers to debug and resolve issues. Document modeling and verification strategies and results. Required Skills : Good coding skill in Verilog(VAMS) / SV real number models. Strong understanding of digital and analog design concepts. Familiarity with SystemVerilog and UVM methodology. Exposure to real number modeling (wreal, AMS modeling concepts). Basic scripting skills (Python, Perl, or Shell). Good problem-solving and communication skills. Project experience in mixed-signal design or verification. Knowledge of simulation tools like Cadence / Xcelium, Synopsys VCS, or Mentor Questa. Interested,please share your updated resume to