Senior Design verification Engineer

Skills :

SOC Verifcation, ASIC Verification, Design Verification, Universal Verification Methodology (UVM), Open Verification Methodology, System Verilog,

Senior RTL Verification Lead / RTL Verification Engineer

Are you an experienced RTL Verification professional looking for your next challenge Look no further!

Qualifications

• BE / ME / MTech / MS in Electrical Engineering
• 6 to 12 years of RTL verification experience for the Senior RTL Verification Lead position
• 4 to 5 years of relevant industry experience for the RTL Verification Engineer position
• Proficiency in advanced verification methodologies like UVM / OVM / VMM / System Verilog
• Experience in constrained random stimulus generation, assertion-based verification, and functional coverage techniques.
• Knowledge of register verification standards, NLP / GLS verification flows
• Strong experience in IP level and sub-system level verification on protocols such as PCI-E, UCIe, HBM, etc.
• Relevant experience in enabling and verifying controller interoperability testing at the sub-system level is a plus

Responsibilities

Experience

If you meet the qualifications and are ready to make a difference, apply now! Send your resume to

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Skills Required

Design Verification, Asic verification, rtl verification , System Verilog