DV Engineer

JD :

Power-aware verification with UPF annotated

Various power scenarios verification

Power vector generation for leakage, sleep, clock tree, and active use cases

Clock verification (Freq, spec compliance, Glitch analysis, Multiple cycle paths)

Reset verification (reset glitch analysis)

Power switch coverage analysis

Strong DV knowledge, SV, UVM based test development

Power-aware verification - UPF based RTL simulation

Power intent understanding

Power-aware GLS with PG netlist

Clock, reset architecture understanding for SoCs