AI-Driven Verification Engineer

Staff Verification Engineer - VLSI and AI Expert

We are seeking a highly skilled staff verification engineer to lead verification efforts for complex SoCs / IPs while collaborating with cross-functional teams on next-generation multimedia and AI-driven system use cases.

The ideal candidate will have proven expertise in developing / maintaining SystemVerilog / UVM-based testbenches, UVCs, sequences, checkers, coverage models, and HVL : SystemVerilog (UVM), SystemC (preferred).

A strong understanding of OOP concepts, leadership, collaboration, debugging & architecture knowledge is also required.

This role involves developing, optimizing, and deploying AI models for audio and video applications, performing model evaluation, quantization, and compression to enable fast and robust inference on embedded hardware.

Key Responsibilities :

• Developing and maintaining SystemVerilog / UVM-based testbenches, UVCs, sequences, checkers, coverage models, and HVL : SystemVerilog (UVM), SystemC (preferred)
• Leveraging strong understanding of OOP concepts, leadership, collaboration, debugging & architecture knowledge
• Deploying AI models for audio and video applications, performing model evaluation, quantization, and compression

Requirements :

Benefits :

About the Role :

This is an exciting opportunity to join our team as a Staff Verification Engineer and contribute to the development of cutting-edge technology.

We offer a dynamic and collaborative work environment, with opportunities for professional growth and development.

If you are a motivated and experienced verification engineer looking to take your career to the next level, we encourage you to apply.