RTL Lead

We're Hiring – RTL Lead (8–12 Years | Bangalore & Hyderabad)

Are you an experienced SoC RTL Design Engineer ready to take technical ownership and lead design execution

We're looking for a passionate RTL Lead to join our dynamic team!

Location : Bangalore & Hyderabad

Experience : 8 – 12 Years

Notice Period : Maximum 1 Month

Key Responsibilities

• Lead SoC RTL design and integration activities
• Write RTL in Verilog and System Verilog
• Work on ARM architecture–based SoC design
• Deep understanding of ARM bus protocols (CHI, AXI, AHB, APB, PCIe)
• Integrate PCIe and Ethernet IPs , chip IOs
• Perform design static checks ( Lint, CDC, RDC, CLP, UPF )
• Collaborate using GIT and related design management tools
• Drive SoC design flows and guide team members on SoC execution
• Participate in technical reviews and design optimization

Qualifications

Mandatory Skills

Interested candidates can share their updated resume at [HIDDEN TEXT] with the subject line :

'Application for RTL Lead – [Your Name]'

Skills Required

Verilog, systemverilog, Pcie, Ethernet