SMTS Silicon Design Engineer

As a Synthesis design engineer, you will work with architects / designers for IP development

KEY RESPONSIBILITIES :

• Design synthesis : Performing logical and physical synthesis of blocks in IP
• Design analysis : Analyzing and verifying that the design meets requirements for functionality, performance, and area
• Design constraints : Defining synthesis design constraints and resolving STA issues
• Timing analysis : Analyzing timing arc and liberty quality, and providing suggestions for fixing timing violations
• Design quality checks : Completing all design quality checks and data quality checks (CDC / RDC / LINT / No clock flops etc)
• Collaboration : Working with RTL engineers to fix timing issues
• Tool evaluation : Driving new tool evaluation and methodology refinement
• ECO Implementation : Develop / enhance auto ECO generation scripts for timing closure and ECO implementation
• Power : Low power optimizations / UPF

PREFERRED EXPERIENCE :

Synthesis engineers should have prior experience with :

Skills Required

Synthesis, Constraints, cdc, Verilog