Job description
Responsibilities :
Test bench design and implementation.
Test coverage plan definition.
Constrained random test development.
Coverage specification analysis.
Automation of the regression test suite
Desired technical skills :
Proficiency in OOPs, Verilog System Verilog.
Solid verification skills : planning, problem solving, debug, adversarial testing and random testing.
Project based work experience with UVM / VMM methodologies.
Candidate must have experience with architecting the testplan test bench.
Hands on experience with Ethernet based protocols, PCIe, AXI, memory controllers, OTN, I2C, SPI, UART etc..
Skills Required
Design Verification, Ethernet, Simulation, Automation
Verification Engineer • Bengaluru / Bangalore