AMS Verification Engineer

Position : AMS Verification Engineers

Experience : 5+ Years

Location : Bangalore, Hyderabad, Ahmedabad, Noida

Key Responsibilities :

Lead the planning, development, and execution of AMS verification strategies for analog / mixed-signal IPs and SoCs.

Define and implement verification plans, including testbenches, stimulus generation, and checking strategies.

Develop and maintain SystemVerilog, Verilog-AMS, or UVM-based verification environments.

Perform co-simulation of analog / digital designs using industry tools (e.g., Cadence, Synopsys, Siemens EDA).

Conduct mixed-signal simulations, behavioral modeling of analog blocks, and integration into top-level environments.

Collaborate with analog designers to create AMS behavioral models (e.g., Verilog-A / AMS) for early integration and verification.

Debug complex AMS simulation issues across multiple abstraction levels.

Drive coverage analysis and sign-off using functional, formal, and assertion-based methods.

Mentor and guide junior engineers in best practices, methodologies, and tool usage.

Ensure verification deliverables meet project timelines and quality standards.