Senior DFT Engineer

DFT Engineer

Experience : 3 years

Location : Bangalore

Develop and implement DFT architecture for ASIC / SoC designs.

Insert and verify scan chains, boundary scan (JTAG), MBIST, LBIST, and other test structures.

Collaborate with RTL and physical design teams to ensure seamless integration of DFT features.

Generate and validate test patterns using ATPG tools for stuck-at, transition, and path delay faults.

Perform fault simulation and coverage analysis to optimize test quality.

Support silicon bring-up and debug of test-related issues.

Work with ATE teams to develop test programs and support production testing.

Interested,please drop your updated resume to janagaradha.n@acldigital.com