Senior / Staff / Sr Staff Design Verification Engineer

Job description

In this role, you will be creating UVM testbenches for a SoC and IP, as well as tests, regressions, and functional coverage to achieve zero bug escapes.

You will interface with the designers to develop the test plans, and from that develop testcases and coverage to thoroughly verify the RTL.

Your regressions will grow to cover the full functionality of the design relative to the architectural simulator and will include corner case testing for the more challenging cases.

Your test and coverage reviews will ensure key coverage.

ESSENTIAL DUTIES AND RESPONSIBILITIES :

Create UVM testbenches, tests, and constraints to ensure design correctness

Design, develop, and maintain modular and reusable UVM testbenches for blocks

Collaborate with colleagues to develop test plans

Create randomized tests, adding constraints and directed tests to fully cover functionality

Confirm test completeness through code and functional coverage

Review testbenches, tests, and coverage with designers, architects, and SW engineers

Integrate tests and coverage within full environment

Write C based BareMetal code for SoC level verification

Relevant experience of 3-10 years