Memory Circuit Design Engineer

Role : Memory Circuit Design Engineer

Experience : 9 to 12 Years

Location : PAN INDIA

Job Description :

• Digital Full Custom CKT Design
• Bitcell Design
• Design of simpler memory blocks (decoding, rowdec, SA, IO block w / o RA, WA)
• Design of complex blocks like RA, WA, Rd selftime and write selftime
• SPRAM / Dual Port / ROM architecture
• Exploring and providing new ckt design and memory architectures – Nice to have
• Library CKT verification at Compiler level
• Sense Amp Analysis(offset, pulse width, glitch, coupling etc.)"
• Read / Write Selftime Analysis
• Functional / Power Marginality analysis
• Latch analysis
• ESPCV
• Power ON and power sequencing checks
• Extraction, IR / EM analysis, PERC etc. – Nice to have
• Library CKT Char and Char verification
• Timing, power, leak etc. setups(definitions, stimuli, MCF etc.)
• Timing, power, leak etc. verification (new addition)
• LVF analysis and implementation
• Critical Path Tight Stimuli (CPTS)
• Full Cut Tight Stimuli (FCTS)
• FC power, timing, power, leak and comparison with CP
• Decoupling CAP
• Ageing (char)
• Concept of Grid – Concept should be known; methodology can be different in diff organizations
• Infrastructure, Packaging & Delivery – ST Methodology will be trained separately
• CAD Tools (More conceptual knowledge needed, tools can be different)
• Global BIST solutions e.g., MASIS, IR Drop solutions, AVM, RedHawk etc.
• Simulators e.g., XA, Eldo
• High sigma analysis (eldo FFP etc.)