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Senior Analog Layout Engineer-High Speed Analog Chip TSMC 5nm

Senior Analog Layout Engineer-High Speed Analog Chip TSMC 5nm

ConfidentialIndia
4 days ago
Job description

Job Title : Senior Analog Layout Engineer High-Speed Analog Chip (TSMC 5nm)

Experience : 8+ Years

Location : Remote / India (must support USA / Canada time zone)

Travel : Willing to travel to the U.S. for project release (as required)

Role Overview

We are looking for a Senior Analog Layout Engineer to work on a high-speed analog chip development in advanced TSMC 5nm technology. The candidate will operate as an individual contributor, responsible for delivering complex high-speed analog and mixed-signal layout blocks with minimal supervision.

This role demands deep technical expertise in chip-level integration, bump planning, and ESD implementation, along with a good understanding of circuit simulation concepts. The engineer will work closely with SoC, Circuit, and Digital teams to ensure robust layout quality and performance.

Key Responsibilities

  • Own end-to-end schematic-to-layout design for high-speed analog and mixed-signal circuits.
  • Perform floor planning, bump and pad-ring design, and ESD implementation at the chip level.
  • Collaborate with SoC, circuit, and digital design teams for layout integration and signoff.
  • Ensure layouts meet all DRC, LVS, ERC, EM / IR and reliability standards.
  • Handle layout matching, shielding, and parasitic optimization for high-speed performance.
  • Support simulation correlation and assist in debugging layout-related circuit issues.
  • Work independently, taking full ownership of assigned IPs and layout deliverables.

The ideal candidate should have a strong understanding of chip-level layout planning, bump design, ESD implementation, and parasitic optimization, along with a basic understanding of circuit simulation. You'll work closely with SoC, circuit, and digital design teams, contributing as an individual contributor in a fast-paced, global environment.

Skills Required

Hands-on experience with TSMC 5nm, Cadence Virtuoso, Calibre / PVS

Strong background in high-speed analog IPs

Expertise in floorplanning, ESD, bump planning, shielding, and matching

Excellent communication and ability to coordinate with global teams

Skills Required

floorplanning, shielding , Cadence Virtuoso, matching

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