Job Title : Senior Analog Layout Engineer High-Speed Analog Chip (TSMC 5nm)
Experience : 8+ Years
Location : Remote / India (must support USA / Canada time zone)
Travel : Willing to travel to the U.S. for project release (as required)
Role Overview
We are looking for a Senior Analog Layout Engineer to work on a high-speed analog chip development in advanced TSMC 5nm technology. The candidate will operate as an individual contributor, responsible for delivering complex high-speed analog and mixed-signal layout blocks with minimal supervision.
This role demands deep technical expertise in chip-level integration, bump planning, and ESD implementation, along with a good understanding of circuit simulation concepts. The engineer will work closely with SoC, Circuit, and Digital teams to ensure robust layout quality and performance.
Key Responsibilities
The ideal candidate should have a strong understanding of chip-level layout planning, bump design, ESD implementation, and parasitic optimization, along with a basic understanding of circuit simulation. You'll work closely with SoC, circuit, and digital design teams, contributing as an individual contributor in a fast-paced, global environment.
Skills Required
Hands-on experience with TSMC 5nm, Cadence Virtuoso, Calibre / PVS
Strong background in high-speed analog IPs
Expertise in floorplanning, ESD, bump planning, shielding, and matching
Excellent communication and ability to coordinate with global teams
Skills Required
floorplanning, shielding , Cadence Virtuoso, matching
Senior Analog Layout • India