Analog Mixed Signal Design Verification

Basic Requirements

• Strong understanding of electrical engineering and digital logic fundamentals
• Hands-on experience in mixed-signal (AMS) verification using schematic, model, and RTL combinations
• Experience with analog behavioral modeling using Verilog AMS, Verilog-A, Wreal
• Good debugging skills in analog design and simulation
• Basic knowledge of SystemVerilog / UVM
• Experience with Cadence tools / simulators is preferred
• Basic scripting skills in Shell, Python, or Perl
• Excellent problem-solving, communication, and presentation skills
• Ability to work collaboratively in a team environment

Primary Responsibilities

Preferred Qualifications

Skills Required

systemverilog, Uvm, Verilog AMS, gls