SOC Verification engineers (SI80FT RM 3512)

Roles and Responsibilities

• Develop and maintain verification testbenches for SoC-level simulation and validation
• Create detailed verification plans based on design specifications and architectural documents
• Implement and run directed and constrained-random tests using SystemVerilog and UVM
• Debug RTL and gate-level simulations to identify and resolve design and testbench issues
• Contribute to regression testing, coverage analysis, and sign-off activities
• Work closely with cross-functional teams including design, DFT, and firmware engineers
• Support post-silicon bring-up and validation when required

Requirements

Skills Required

Vcs, Questa, Python, Perl, Dft