Design Verification Engineer - SoC / UVM

We are seeking a highly skilled and experienced Design Verification Engineer to join our growing team in Bangalore. The ideal candidate will have hands-on expertise in IP or subsystem verification of complex SoC components, using SystemVerilog and UVM methodologies. A strong background in interconnect / fabric verification and industry-standard protocols is essential.

Key Responsibilities :

• Own and execute IP-level or subsystem-level verification for complex digital designs.
• Develop and maintain SystemVerilog / UVM-based testbenches, test plans, and functional coverage models.
• Implement assertions, checkers, and constrained-random verification environments.
• Verify Fabric / NOC / Interconnect blocks with high complexity.
• Work on verification of industry-standard protocols like AMBA (AXI / ACE), PCIe, CXL, etc.
• Collaborate with architects and designers to understand design intent and derive effective verification strategies.
• Analyze and debug functional and performance issues in simulation.
• Contribute to regression infrastructure and test automation.
• (Optional) Verify coherent traffic and implement related test scenarios.

Required Skills :

Preferred Qualifications :

(ref : hirist.tech)