Lead Design Verification engineer (IP)

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Lead Verification Engineer THE ROLE : The focus of this role is to plan, build, and execute the verification plan for AMD's FPGA IPs, resulting in no bugs in the final design. THE PERSON : You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites / timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES : Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics - modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE : Proficient in IP level ASIC verification. Knowledge of PCIe, CXL or other IO protocol is preferred Experience with DMA verification is preferred Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools / process Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience : Perl, Ruby, Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions. ACADEMIC CREDENTIALS : Bachelors or Masters degree in computer engineering / Electrical Engineering Benefits offered are described : AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.Lead Verification Engineer THE ROLE : The focus of this role is to plan, build, and execute the verification plan for AMD's FPGA IPs, resulting in no bugs in the final design. THE PERSON : You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites / timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES : Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics - modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE : Proficient in IP level ASIC verification. Knowledge of PCIe, CXL or other IO protocol is preferred Experience with DMA verification is preferred Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools / process Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience : Perl, Ruby, Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions. ACADEMIC CREDENTIALS : Bachelors or Masters degree in computer engineering / Electrical Engineering Benefits offered are described : AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.