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Senior Design Verification Engineer-Onsite (12 / 10 / 2025)

Senior Design Verification Engineer-Onsite (12 / 10 / 2025)

BITSILICAHyderabad, Telangana, India
2 hours ago
Job description

Over 10 years of digital IP verification, advanced knowledge of ASIC / SOC Design flow and state of the art verification flow

Proficient with Verilog, System Verilog and UVM.

  • Good in UVM concepts and SystemVerilog language. (SVA, UVM scoreboard)
  • Good in defining and developing UVM based verification frameworks, testbenches, processes and flows.
  • Good in working in Linux and Windows environments.
  • Familiarity with power aware simulation and firmware / hardware co-verification is a plus.
  • Familiarity with industry standard high-speed protocols such as USB, PCIE, UFS, SATA, Ethernet is a plus.
  • Familiarity with industry standard interconnects such as AMBA (AXI, APB, AHB) is a plus.
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Design Verification • Hyderabad, Telangana, India

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