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Senior Design Verification Engineer

ConfidentialHyderabad / Secunderabad, Telangana, India

9 days ago

Job description

Job Location : Hyderabad

Experience Level 5+ years

The position involves designing, developing and deploying UVM based reusable testbenches for RTL unit blocks, sub-system level and top-level systems with emphasis on

verifying the functionality and generating the code / functional coverage reports. The candidate should come up with test plans and test cases in order to achieve 100% code coverage and functional coverage.

Educational Qualification :

Bachelor major in electronics, embedded programming, ECE, EEE.

Key Requirements :

Experience in ASIC / FPGA verification using System Verilog.

Develop and sign off on test plans and test cases.

Strong knowledge of digital design, Verilog, System Verilog, UVM, C / C++.

Experience in AMBA AHB / AXI / APB based IPs design / verification.

Experience in usage of assertions, constrained random generation, functional and code

Coverages.

Experience in FPGA design and FPGA EDA tools will be a plus.

Experience in scripting, such as TCL, Perl, Bash and python to automate the verification

Methodologies and flows.

Able to build and set up scalable simulation / verification environments.

Ability to focus on finding the design issues and corner cases.

Knowledge of version control systems (GIT is preferable).

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Skills Required

FPGA Design, C, Bash, Uvm, code coverage , AMBA, Git, Axi, APB, Perl, Verilog, AHB, System Verilog, Python, Tcl

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Senior Design Verification Engineer • Hyderabad / Secunderabad, Telangana, India