Senior Design Verification Engineer- Singapore

Over 4 years of experience in digital IP verification, with advanced knowledge of ASIC / SOC design flow and modern verification methodologies.

About the Role

Proficient in Verilog, SystemVerilog, and UVM. Strong understanding of UVM concepts and SystemVerilog features (SVA, UVM Scoreboard).

Responsibilities

Skilled in defining and developing UVM-based verification frameworks, testbenches, processes, and flows.

Exposure to high-speed protocols such as USB, PCIe, UFS, SATA, Ethernet (plus).

Knowledge of AMBA interconnects (AXI, APB, AHB) (plus).

Qualifications

Over 4 years of experience in digital IP / SOC verification.

Required Skills

Advanced knowledge of ASIC / SOC design flow.

Proficient in Verilog, SystemVerilog, and UVM.

Strong understanding of UVM concepts and SystemVerilog features (SVA, UVM Scoreboard).

Preferred Skills

Exposure to high-speed protocols such as USB, PCIe, UFS, SATA, Ethernet.

Knowledge of AMBA interconnects (AXI, APB, AHB).