RTL FPGA Design Engineer (3 Days Left)

RTL FPGA Design Engineer

Experience : 2-4 years

Location : Hyderabad

FPGA architecture

Vivado Flow

Scripting and automation

Verilog / VHDL

HW debugging

We are looking for some background of scripting and or conceptual understanding of Power for experienced candidates.

Interested,please share your updated resume to janagaradha.n@acldigital.com