Design Verification Engineer

We need experienced engineers to verify an IP / full-chip using System Verilog / UVM. Expertise in PCIe / DDR verification is preferable at IP / chip level.

Skills :

• Overall 3+ years industry experience in Design Verification using System-Verilog / C / UVM.
• Generic knowhow on Digital Design and Verification methodologies.
• Experience in System Verilog / UVM based IP / SoC verification using advanced technologies.
• Good understanding of Constraint based Random verification;
• VIP coding;
• Test Plan design;
• Test cases coding;

Coverage strategies and measurement

Verilator).

Traits :

Execution minded