System Verification Engineer - System Verilog

his is what you are responsible for :

• Develop and maintain verification plans, testbenches, and test cases for ASIC designs.
• Collaborate with design and architecture teams to understand design specifications and requirements.
• Design and implement System Verilog / UVM-based verification environments.
• Create and execute test cases to verify functionality, performance, and compliance with specifications.
• Debug failures and drive issues to closure, working closely with cross-functional teams.
• Mentor junior team members and provide technical guidance.
• Contribute to the continuous improvement of verification methodologies and best practices.
• Create and maintain verification environments for SOCs.

Necessary Qualifications :

Preferred Qualifications :

(ref : hirist.tech)