Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC / LVS), PDN, Timing Closure and power optimization.
Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions.
Knowledge in timing convergence of high frequency data-path intensive Cores and advanced STA concepts
Knowledge in Block level PnR convergence with Synopsys ICC2 / Cadence Innovus and timing convergence in PTSI / Tempus
Good understanding of clocking architecture.
Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc.
Good knowledge of Tcl / Perl Scripting
Strong problem-solving skills and good communication skills.
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Design Engineer • Chennai, IN
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