This role is for an RTL Design Engineer to contribute to IP and sub-system development and integration. The ideal candidate will have hands-on experience in logic design, RTL coding, and either ASIC or FPGA implementation, with a focus on creating high-performance digital designs.
Responsibilities
- Responsible for IP / sub-system level micro-architecture development and RTL coding .
- Prepare block / sub-system level timing constraints .
- Integrate IP / sub-system into larger designs.
- Perform basic verification in either an IP Verification environment or on an FPGA.
Skills
Required Skills :
Expertise in Verilog .Experience in Logic design / micro-architecture / RTL coding .Knowledge of AMBA protocols - AXI, AHB, APB .Experience in Synthesis / Understanding of timing concepts for ASIC or experience in Xilinx FPGA Design Implementation .Hands-on experience in Multi Clock designs and Asynchronous interfaces .Experience on tools utilized in all phases of ASIC development such as Lint, CDC, Simulation , etc.Preferred Skills :
Experience in design of DDR / USB / PCIe controller or other complex protocols.Knowledge of low power concepts .Qualifications
A B.Tech. or M.Tech. degree.Immediate availability is preferred.Skills Required
Design Engineering, Microarchitecture, RTL Coding, Verilog, Logic Design