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RTL Design Engineer - PCI-e

RTL Design Engineer - PCI-e

ARISE TECHGLOBAL PRIVATE LIMITEDBangalore
13 days ago
Job description

Job Description :

We are looking for a highly skilled RTL Design Engineer with strong expertise in RTL coding, micro-architecture design, CDC, and lint checks, and hands-on experience in PCIe Gen4 / Gen5 (Root Complex / PCIe Controller) development. The candidate will be responsible for end-to-end design implementation, ensuring high-quality, synthesizable RTL, and collaborating closely with verification and architecture teams.

Key Responsibilities :

  • Design and develop RTL modules for PCIe Gen4 / Gen5 Root Complex and Controller.
  • Translate architecture specifications into micro-architecture and implement high-quality RTL.
  • Perform Clock Domain Crossing (CDC) analysis and resolve issues.
  • Conduct lint, synthesis checks, and timing closure support to ensure design robustness.
  • Collaborate with verification teams to define verification strategies and resolve design bugs.
  • Work on design integration at IP / Sub-system / SoC level.
  • Support DFT / STA / physical design teams for successful chip implementation.
  • Ensure compliance with PCIe protocol specifications and performance requirements.
  • Document design, micro-architecture, and review specifications.

Required Skills & Experience :

  • Strong expertise in RTL Design (SystemVerilog / Verilog).
  • Hands-on experience in micro-architecture design and documentation.
  • Deep understanding of Clock Domain Crossing (CDC) methodologies and tools.
  • Experience with linting tools (Spyglass, Ascent Lint, etc.).
  • Solid exposure to PCIe Gen4 / Gen5 protocols - must have worked on Root Complex and / or Controller.
  • Experience in synthesis, timing closure, and debug.
  • Strong problem-solving, debug, and analytical skills.
  • Good communication and ability to work with global teams.
  • Nice to Have :

  • Exposure to other high-speed interfaces (CXL, Ethernet, DDR, USB).
  • Familiarity with low-power design, power intent (UPF / CPF).
  • Knowledge of Emulation / FPGA prototyping.
  • Scripting knowledge (Python / Perl / Tcl) for automation.
  • SoC-level integration and design experience.
  • Education : Bachelor's / Master's degree in Electronics, Electrical, or Computer Engineering or equivalent.

    (ref : hirist.tech)

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