Sr Principal Design Engineer

Description

• Design Verification role for IP development team.
• B. Tech / M.Tech with 10+ years of relevant experience.
• Position is based in Bangalore / Noida, part of Cadence IP Group.
• Verification role for Serial and Interface Design IPs verification (PCIe, CCIX, CXL, USB, Ethernet, SATA / SAS, UFS, SPI, HDMI, MIPI, I3C)
• UVM testbench development to build a robust, scalable and efficient testbench to verify the design IPs.
• In addition to UVM functional verification, role could involve Formal verification of complex design modules.
• In addition to UVM functional verification, role could involve participating in Emulation qualification of design IPs.
• Understand design and produce detailed verification strategy and test plan.
• Self-starter and learner with passion for getting the job done on time with great quality.
• Strong problem solving, analytical and debug skills
• Excellent verbal and written communications skills
• Clearly communicate project status, issues etc.

Behavioral skills required :

We’re doing work that matters. Help us solve what others can’t.