Join us in building next-generation CPUs and AI / ML hardware. In this role, you’ll focus on creating high-quality stimulus content across pre-silicon, emulation, and post-silicon stages to validate complex CPU microarchitectures. You’ll work closely with design, verification, and post-silicon teams to ensure robust and reusable test scenarios.This role is hybrid , based out of Bengaluru,India.We welcome candidates with 7+years of experience for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.Who You AreYou have experience with out-of-order CPU microarchitecture, especially around load / store, caches, and memory systemsYou’re comfortable working across pre-silicon, emulation, and post-silicon environmentsYou’ve written and debugged stimulus on x86, ARM, or RISC-V architecturesYou enjoy working closely with cross-functional teams to recreate bugs and improve test coverageWhat We NeedDevelop reusable stimulus at core, cluster, and system levels across multiple environmentsWork with design and verification teams to validate CPU architectural and microarchitectural featuresCreate and maintain testplans and coverage for RISC-V architecture featuresSupport post-silicon validation by bringing up stimulus in lab and emulation setups
Design Verification Engineer • Bengaluru, Karnataka, India