Staff engineer, design verification

Join us in building next-generation CPUs and AI / ML hardware. In this role, you’ll focus on creating high-quality stimulus content across pre-silicon, emulation, and post-silicon stages to validate complex CPU microarchitectures. You’ll work closely with design, verification, and post-silicon teams to ensure robust and reusable test scenarios.

This role is hybrid , based out of Bengaluru, India.

We welcome candidates with 7+years of experience for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

You have experience with out-of-order CPU microarchitecture, especially around load / store, caches, and memory systems

You’re comfortable working across pre-silicon, emulation, and post-silicon environments

You’ve written and debugged stimulus on x86, ARM, or RISC-V architectures

You enjoy working closely with cross-functional teams to recreate bugs and improve test coverage

What We Need

Develop reusable stimulus at core, cluster, and system levels across multiple environments

Work with design and verification teams to validate CPU architectural and microarchitectural features

Create and maintain testplans and coverage for RISC-V architecture features

Support post-silicon validation by bringing up stimulus in lab and emulation setups