Design Verification Engineer

Boltchip is a Consulting firm based in Singapore building Innovation Capability Centers (ICCS) for global clients. One of our US clients is building their products on NOC and having IPS in front end design is expanding their team in Bhubaneshwar and Bangalore India.

Position : Verification Engineer

Experience : 4–6 years

Location : Bangalore / Bhubaneswar

Qualification : B.Tech / M.Tech in Electronics or related field

About the Role

We are seeking skilled Verification Engineers with strong experience in SoC design verification. The candidates should have expertise in verifying complex SoC-level designs, with exposure to industry-standard protocols and verification methodologies(UVM). He / She will be part of a dynamic team working on state-of-the-art SoC projects, contributing to verification planning, test bench development, execution, and closure.

Key Responsibilities

Develop, implement, and maintain verification environments using SystemVerilog and UVM.

Perform test planning, test case development, debugging, and functional coverage closure.

Verify SoC-level integration of IPs and subsystems.

Work closely with design, architecture, and validation teams to ensure first-pass silicon success.

Drive verification strategies, regression automation, and debug complex failures.

Required Skills & Experience

4–7 years of experience in ASIC / SoC functional verification.

Strong hands-on expertise with SystemVerilog and UVM methodology.

Solid experience in SoC verification including bus / protocol-level testing.

Good understanding and working knowledge of standard protocols such as :

AMBA (AXI / AHB / APB)

UART, SPI, I2C / I3C

MIPI, and other SoC-relevant protocols

Experience in developing and debugging complex test benches.

Familiarity with coverage-driven verification and constrained-random testing.

Proficiency with simulation, waveform debug, and regression tools.

Strong problem-solving, analytical, and communication skills.

Preferred Skills (Good to Have)

Exposure to low-power verification (UPF).

Experience with gate-level simulations and formal verification.

Knowledge of scripting (Perl / Python / Shell) for automation.

Experience with verification of subsystems such as USB subsystem, UCIe, PCIe / CXL subsystem, memory controllers, interconnects, or peripheral IPs.