Principal SoC Design Verification Methodology Engineer

Principal Gen AI based SoC Design Verification Methodology Engineer

We are a US based Stealth mode Start-up

location : Hyderabad / Bangalore / Remote ( any where in India )

We unify the processes used in Semiconductor and Hardware Systems design - thus reducing bugs, improving efficiency and productivity

Our breakthrough technology has drawn investment from Silicon Valley’s boldest VCs and semiconductor pioneers. Beyond capital, they bring decades of expertise and powerful networks,

Senior Application Engineer, AI based CAD systems

This role offers an exceptional opportunity to lead product definition, validation and customer engagement.

Key Responsibilities :

Work with the software development team to define the detailed feature requirements

Create and execute validation plans for the features

Work with multi-functional and distributed team to drive issues and features to closure

Develop end-to-end flows on sample designs / scenarios and collaterals / demos

Who you are :

BS / MS in Electronics or equivalent

10-12+ years of working experience in SoC DV or IP design for high speed interfaces

Proven experience in working with System Verilog / UVM / IP Exact / System RDL

Experience in defining hardware design / verification plans

Git, CI / CD, Linux Scripting, Tcl, Python

Contact : Uday

Mulya Technologies

'Mining The Knowledge Community'