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Design Verification Engineer
Design Verification EngineerConfidential • India, Aurangabad
Design Verification Engineer

Design Verification Engineer

Confidential • India, Aurangabad
5 hours ago
Job description

Experience : 3.00 + years

Salary : INR 2680000-3750000 / year (based on experience)

Expected Notice Period : 15 Days

Shift : (GMT+05 : 30) Asia / Kolkata (IST)

Opportunity Type : Remote

Placement Type : Full Time Permanent position(Payroll and Compliance to be managed by : Architect Labs)

  • Note : This is a requirement for one of Uplers' client - Architect Labs)

What do you need for this opportunity

Must have skills required :

Data Analytics, emulation, Tape-out, SystemVerilog, testbench, UVM / OVM, VCS, Python, design verification, SoC Design

Architect Labs is Looking for :

Responsibilities

  • Create detailed test plans based on design specifications
  • Specify and build a UVM-based validation infrastructure for POC designs.
  • Develop directed and random test cases to thoroughly test the design.
  • Execute simulations and analyze results to identify and debug RTL / Verif bugs.
  • Analyze simulation logs, coverage reports, waveform traces, and generate convergence data for AI models.
  • Label, categorize verification outcomes (pass / fail, assertion hits, coverage, etc.)
  • Identify, classify, tabulate, and generate analytics for DV bug / fix patterns.
  • Help in prompt-tuning, generating rules, and guardrails for our RTl coding agents and models.
  • Collaborate with ML engineers to build evaluation datasets, internal benchmarks, and
  • evaluate model behavior and performance on verification tasks.

    Requirements

  • Bachelor''s (or more) degree; 3+ years of experience in design / IP verification flows.
  • Proficiency in System Verilog & standard verification methodologies (UVM, OVM)
  • Experience with simulation and debugging tools like VCS, Xcelium, Verdi, etc..
  • Experienced in test-bench, stimuli, checkers, score-boards, and monitors development
  • Familiarity with coverage methodology, signature, and bug analysis
  • Scripting skills in Python / Perl for test automation
  • Familiarity with SoC integration and design principles.
  • Prefered :

  • Experienced in at least one product-level tape-out.
  • Data analytics skills, data annotation experience.
  • Flexibility in work hours, sync with PST timeline when needed.
  • Experience in Emulation methodology and tool flow.
  • Collaboration & Time Zone

  • You'll work remotely from India but collaborate daily with the Palo Alto team.
  • Must have excellent written and spoken English communication, clear, concise, and proactive.
  • Expect regular standups and sprint syncs with California (typically between 8–11 PM IST / 7–10 AM PST).
  • We value responsiveness, initiative, and a sense of ownership that transcends time zones.
  • How to apply for this opportunity

  • Step 1 : Click On Apply! And Register or Login on our portal.
  • Step 2 : Complete the Screening Form & Upload updated Resume
  • Step 3 : Increase your chances to get shortlisted & meet the client for the Interview!
  • About Uplers :

    Our goal is to make hiring reliable, simple, and fast. Our role will be to help all our talents find and apply for relevant contractual onsite opportunities and progress in their career. We will support any grievances or challenges you may face during the engagement.

    (Note : There are many more opportunities apart from this on the portal. Depending on the assessments you clear, you can apply for them as well).

    So, if you are ready for a new challenge, a great work environment, and an opportunity to take your career to the next level, don't hesitate to apply today. We are waiting for you!

    Skills Required

    Emulation, Vcs, Ovm, Design Verification, SOC design, Uvm, Data Analytics, systemverilog, Python

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    Design Verification Engineer • India, Aurangabad

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