Lead Sta & Synthesis Design Engineer

BE / Btech EXp- 5- 12 Yrs

Work on challenging DDR PHY IP & Testchip Physical Design from Netlist-to-GDS in tech nodes below 7nm.

• Take ownership of one or more physical design blocks includes all of, floorplan, CTS, PNR, QRC, STA, PV & IR.
• Contribute to design methodology, flow automation.
• Innovate & implement Power, Performance and Area optimization techniques.
• Participate in IP release to customers and support team on standardize & document learnings.

Key Skills : Netlist-GDS physical design, 7nm+ Technology nodes, CTS and Custom Clocking, STA, PV, scripting tcl & python.

Minimum qualifications :

Preferred qualifications :